Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc.) has been built up around this technology.
In this process, a photomask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics that project light coming through the photomask to image the circuit pattern, typically with a 4× to 5× reduction factor, on a photo-resist film formed on a wafer. The term “chrome” refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material on the photomask may also vary, such as in the case of an attenuating phase shift mask.
The process of making the photomask begins by receiving data from a design database. The design database contains data describing at least a portion of an integrated circuit design layout, referred to as the “drawn” pattern, which generally provides a target pattern that the designers wish to achieve on the wafer. Techniques for forming design databases are well known in the art.
After receiving the design database, mask makers form one or more photomasks that can be used to implement the target pattern described by the design data. This mask making process may generally include generating mask pattern data describing initial photomask patterns for forming device features. The initial photomask patterns are formed by employing various resolution enhancement techniques. The resolution enhancement techniques can include splitting the drawn pattern so that it is patterned using two or more photomasks, such as a phase shift mask and a trim mask, for use in an alternating phase shift process (“altPSM”). Alternating phase shift processes may also be referred to as strong phase shift or Levinson phase shift technologies. Such resolution enhancement techniques for forming initial photomask patterns from design data are well known in the art.
After the initial photomask patterns are formed, a proximity correction process is carried out that corrects the mask pattern data for proximity effects. The proximity correction process generally involves running proximity correction software to perform calculations that alter the shape of the initial photomask pattern to take into account proximity effects, such as optical diffraction effects that occur during the imaging process. In this method, a computer simulation program is often used to compute image-like model values that are taken to represent the features formed for a particular photomask feature pattern or group of patterns. Based on these simulated model values, the photomask pattern can be altered and then simulated again to determine if the altered pattern will improved the printed features. This process can be repeated until the result is within desired specifications. The features added to a photomask pattern based on this procedure are called optical proximity correction features.
After proximity correction has been performed, verification of the mask pattern data can be performed. This can include running various quality checks to determine whether the photomask patterns generated will form the desired pattern for implementing the circuit specified in the drawn data. The mask pattern data can then be sent to a mask shop, where the actual photomasks are fabricated from the mask pattern data.
One of the most common commercial implementations of alternating phase shift mask technology is the double exposure method. In this method, the critical device features to be patterned are imaged during a first exposure using a first mask, such as a phase shift mask. The non-critical and other secondary features are imaged in a second exposure using second mask, such as a conventional chrome-on-glass mask. In the past, both the first and second exposures were performed on the same photoresist layer.
More recently, a new process has been developed, referred to herein as two-print/two-etch (“2p/2e”) or “double patterning,” in which the first exposure and second exposure are each performed on separate photoresists. The patterns from each of the photoresists can be individually transferred to, for example, a hardmask. In some processes, rather than employing a hardmask, the first and second patterns from the first and second exposures can be transferred directly to the wafer in two separate etch steps.
In an exemplary 2p/2e processes, a phase pattern may be formed in a first photoresist. The phase pattern can then be transferred to a hardmask using an etching technique and the first photoresist removed. A trim pattern can then be formed in a second photoresist and the resulting photoresist pattern is then transferred to the hardmask using a second etching step. Subsequently, the hardmask pattern, having both the phase and trim patterns etched therein, can be used to etch the wafer.
In the past, especially when the first mask of the 2p/2e process was an alternating phase reticle, some inherent properties of the phase mask would form certain features in the resist that, if fully transferred to the layer being formed, were not essential to, or might interfere with, its function. Certain other features may also have been defined by the first mask that have substantially no electrical significance to the circuit, but were employed to improve critical dimension control when forming semiconductor devices by removing or minimizing the differences in OPC and responses to process variations. We shall refer to these features as “ghost features” because they were removed with the processing of the second mask (sometimes called a trim mask because it “trimmed” these features away).
In 2p/2e processes, the removal of the ghost features by the second mask can cause difficulties in patterning. For example, the patterns on the second mask that are used to remove the ghost features can have very small dimensions, and may require employing assist features, such as sub-resolution assist features (“SRAFs”). SRAFs provide diffraction support and are generally well known in the art, as described, for example, in pending U.S. patent application Ser. No. 11/531,048, entitled “Method for achieving compliant sub-resolution assist features,” by Sean O'Brien, the disclosure of which is herein incorporated by reference in its entirety. The placement of the assist features to provide the requisite diffraction support for the patterns used to remove the ghost features may interfere with the placement of other assist features used to provide diffraction support for other substantially important second mask pattern features. Further, the patterns on the second mask used to remove the ghost poly can result in complicated shapes on the second mask. As densities of integrated circuit devices increase, achieving the complicated patterns can be difficult. Accordingly, to achieve increased densities of integrated circuit devices further innovations relating to the 2p/2e processing techniques are desired.